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| May 1997 ML4810*, ML4811** High Frequency Power Supply Controller GENERAL DESCRIPTION The ML4810 and ML4811 High Frequency PWM Controllers are optimized for use in Switch Mode Power Supply designs running at frequencies to 1MHz. The ML4810/11 contain a unique overload protection circuit which helps to limit stress on the output devices and reliably performs a soft-start reset. These controllers are designed to work in either voltage or current mode and provide for input voltage feed forward. A 1.1V threshold current limit comparator provides a cycle-by-cycle current limit. An integrating circuit "counts" the number of times the 1.1V limit was reached. A soft-start cycle is initiated if the cycle-by-cycle current limit is repeatedly activated. A reset delay function is provided on the ML4811. These controllers are similar to the UC1825 controller, however these controllers include many features not found on the 1825. These features are set in Italics. FEATURES s s s s s s s s s s s Integrating Soft Start Reset High current (2A peak) dual totem pole outputs Practical operation to 1MHz (fOSC) 5.1V 2% trimmed bandgap reference Under voltage lockout with 7V hysteresis Soft Start Reset Delay (ML4811) Oscillator synchronization function (ML4811) Soft Start latch ensures full soft start cycle Outputs pull low for undervoltage lockout Accurately controlled oscillator ramp discharge current All timing currents "slaved" to RT for precise control * This part is End of Life as of August 1, 2000 ** This part is Obsolete BLOCK DIAGRAM (Pin numbers shown are for ML4811) 6 7 10 11 8 3 2 1 9 RT CT SYNC O.V.P./SHUTDOWN RAMP E/A OUT NI INV SOFT START P + - OSC 2.2V + - CLOCK 5 1.25V + - R COMP I(1) S Q PWR VC OUT A C TF.F. Q Q POWER GND POWER VC OUT B POWER GND V+ + - ERROR AMP I(1) V+ 16 14 17 15 1.1V - + 4V 1.5V 2.45V 4 RC (RESET) 20 - - RESET DELAY CLOCK + + + + - - 12 ILIM/SD ENABLE VREF VREF GEN Q 9V R - 1.5V VREF 19 S S 3x I(1) Q R INTERNAL BIAS VCC GND 18 5.1V 1.1V 1.1V UNDER VOLTAGE LOCKOUT + 13 3V I(1) = 16 x R T 1 ML4810, ML4811 PIN CONFIGURATION ML4811 20-Pin DIP (P20) 20-Pin SOIC (S20) INV 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ML4810 16-Pin DIP (P16) 16-Pin SOIC (S16W) INV NI E/A OUT RCRESET RT CT RAMP SOFT START 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RESET DELAY 5.1V REF VCC OUTB POWER VC PWR GND OUTA GND ILIM/S.D. OVP 5.1V REF VCC OUTB POWER VC PWR GND OUTA GND ILIM/S.D. NI E/A OUT RCRESET CLOCK RT CT RAMP SOFT START SYNC TOP VIEW TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 2 3 4 5 6 INV NI E/A OUT RCRESET CLOCK RT Inverting input to error amp. Non-inverting input to error amp. Output of error amplifier and input to main comparator. Timing elements for Integrating Soft Start reset. Oscillator output. Timing resistor for oscillator -- sets charging current for oscillator timing capacitor (pin 6). Timing capacitor for oscillator. Non-inverting input to main comparator. Connected to CT for voltage mode operation or to current sense resistor for current mode. 11 OVP 12 ILIM/S.D. 13 GND 14 OUTA Exceeding 2.5V terminates the PWM cycle and inhibits the outputs. Current limit sense pin. Normally connected to current sense resistor. Analog signal ground. High current totem pole output. This output is the first one energized after power on reset. Return for the high current totem pole outputs. Positive supply for the high current totem pole outputs. High current totem pole output. Positive supply for the IC. Buffered output for the 5.1V voltage reference. 15 PWR GND 16 VC 17 OUTB 18 VCC 19 5.1V REF 7 8 CT RAMP 9 SOFT START Normally connected to Soft Start capacitor. A high going pulse terminates the PWM cycle and discharges CT. 10 SYNC 20 RESET DELAY Timing capacitor to determine the amount of delay between fault. 2 ML4810, ML4811 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (Pins 18, 16) ...................................... 25V Output Current, Source or Sink (Pins 14, 17) DC ....................................................................... 0.5A Pulse (0.5s) ......................................................... 2.0A Analog Inputs (Pins INV, NI, SOFT START) ....................... -0.3V to 7V (Pins 9, 10, 11, 12, 20) .............................. -0.3V to 6V Clock Output Current (Pins 5) ................................. -5mA Error Amplifier Output Current (Pin 3) ...................... 5mA Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering 10 sec.) ..................... 260C Thermal Resistance (JA) Plastic DIP ....................................................... 65C/W Plastic SOIC .................................................... 65C/W OPERATING CONDITIONS Temperature Range ML4810, ML4811 ...................................... 0C to 70C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V, RT = 3.65k, CT = 1000pF, TA = Operating Temperature Range. (Note 1) PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak Sync Input Threshold Sync Input Current REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current UNDERVOLTAGE LOCKOUT Start Threshold UVLO Hysteresis ERROR AMPLIFIER Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain 1 < VO < 4V 60 0.6 0.1 96 20 3 1 mV A A dB 15 6.5 16 7 17 7.5 V V TJ = 25C, IO = 1mA 10V < VCC < 25V 1mA < IO < 10mA 0C < TJ < 150C line, load, temperature 10Hz to 10kHz TJ = 125C, 1000 hrs VREF = 0V -15 4.95 50 5 -50 25 -100 5.00 5.10 2 5 0.2 5.20 20 20 0.4 5.25 V mV mV % V V mV mA SYNC = 4V 1.6 0.8 1.0 line, temperature 340 3.9 4.5 2.3 2.8 1.0 2.3 1.4 2.9 TJ = 25C 10V < VCC < 25V 360 400 0.2 5 460 440 4 kHz % % kHz V V V V V V A CONDITIONS MIN TYP MAX UNITS 3 ML4810, ML4811 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER ERROR AMPLIFIER (Continued) CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Slew Rate PWM COMPARATOR Pin 8 Bias Current Duty Cycle Range Pin 3 Zero DC Threshold Delay to Output SOFT-START Charge Current (Pin 9) Discharge Current (Pin 9) Charge Current (Pin 20) Discharge Current (Pin 20) CURRENT LIMIT/SHUTDOWN Pin 12 Bias Current Current Limit Threshold Reset Threshold (Pin 12) Delay to Output Pin 4 Charging Current Restart Threshold (Pin 4) OVP Shutdown Threshold (Pin 11) OVP Input Current Charge Current (Pin 8) OUTPUT Output Low Level Output High Level Collector Leakage Rise/Fall Time SUPPLY Start Up Current ICC Note 1: CONDITIONS 1.5 < VCM < 5.5V 10 < VCC < 30V VPIN 3 = 1V VPIN 3 = 4V IPIN 3 = -0.5mA IPIN 3 = 1mA MIN 65 75 1 -0.5 4.0 0 3 6 TYP 95 90 2.5 -1.3 4.7 0.5 5.5 12 -1 MAX UNITS dB dB mA mA 5.0 1.0 V V MHz V/s VPIN 8 = 0V 0 1.1 -5 75 A % V ns A mA mA mA A 1.25 50 80 -75 ML4811 VPIN 9 = 1V, VPIN 4, 12 = 0 VPIN 9 = 3V, VPIN 4 > 2.5 VPIN 9 = 3V, VPIN 12 > 1.65, VPIN 4 < 2 VPIN 20 = 1V Requires external discharge resistor 0V < VPIN 12 < 4V -35 1 1 1 -55 5 5 5 0 +15 1.2 0.95 1.3 1.1 1.75 1.50 40 150 2.45 2.7 50 -50 0.25 1.2 13.0 12.0 13.5 13.0 100 30 500 60 1.4 1.3 1.90 1.8 70 180 3 2.8 60 -60 0.4 2.2 A V V V V ns A V V A A V V V V A ns ML4810 ML4811 ML4810 ML4811 VPIN 4 < 2V VPIN 4 < 2V VPIN 12 = 2V 1.60 1.4 120 2 2.4 VPIN 11 = 3V ML4810 VPIN 8 = 1V, VPIN 4, 9 = 0 IOUT = 20mA IOUT = 200mA IOUT = -20mA IOUT = -200mA VC = 30V CL = 1000pF ML4810 ML4811 ML4810 ML4811 VCC = 8V VCC = 8V VPIN 1, 7, 9 = 0V, VPIN 2 = 1V, TA = 25C VPIN 1, 7, 9 = 0V, VPIN 2 = 1V, TA = 25C 40 -40 2.0 2.5 32 38 3.5 4.0 46 55 mA mA mA mA Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 4 ML4810, ML4811 FUNCTIONAL DESCRIPTION SOFT START AND CURRENT LIMIT The ML4810/11 offers a unique system of fault detection and reset. Most PWM controllers use a two threshold method which relies on the buildup of current in the output inductor during a fault. This buildup occurs because: 1. Inductor di/dt is a small number when the switch is off under load fault (short circuit) conditions, since VL is small. 2. Some energy is delivered to the inductor since the IC must first detect the over-current because there is a finite delay before the output switch can turn off. TPD TPD TPD A method of circumventing this problem involves "counting" the number of times the controller terminates the PWM cycle due to the cycle by cycle current limit. When the switch current crosses the 1.1V threshold A1 signals the F1 to terminate the cycle and sets F3, which is reset at the beginning of the PWM cycle. The output of F3 turns on a current source to charge C2. When, after several cycles, C2 has charged to 2.45V, A5 turns on F2 to discharge soft start capacitor C1. Charge is short lived (for instance a disk drive start-up or a board being plugged into a live rack) the control can "ride out" the surge with the switch protected by the cycle by cycle limit. R1 and C1 can be selected to track diode heating, or to ride out various system surge requirements as required. If the high current demand is caused by a short circuit, the duty cycle will be short and the output diodes will carry the current for the majority of PWM cycle. C2 charges fastest for low duty cycles (since F3 will be on for a longer time) providing for quicker shutdown during short-circuit when the output diodes are being maximally stressed. VTH2 VTH1 SWITCH CURRENT DIODE CURRENT Figure 1. Current Waveforms for Slow Turn-Off System with Load Fault This scheme was adequate for controllers with longer comparator propagation delays and turn-off delays than is desirable in a high frequency system. For systems with low propagation delays, very little energy will be delivered to the inductor and the current "ratcheting" described above will not occur. This results in the controller never detecting the load fault and continuing to pump full current to the load indefinitely, causing heating in the output rectifiers and inductor. VTH2 VTH1 TPD TPD TPD RESET DELAY 20 V+ QI ERROR AMP A3 I(1) + - FROM OSC. I(1) R SOFT START 9 Q F1 S G2 Q2 - - A4 + - C1 1.1V 2.45V RCRESET 4 FROM PWM COMPARATOR R F2 Q S A5 + QI G1 C2 I(2) SWITCH CURRENT DIODE CURRENT 4UL0 Q F3 R S FROM OSC. R1 1.5V ILIM/SD 12 - A2 + + Figure 2. Current Waveforms for High Speed System with Load Fault 1.1V - A1 Figure 3. Integrating Soft Start Reset 5 ML4810, ML4811 OSCILLATOR The ML4811 oscillator charges the external capacitor (CT) with a current (ISET) equal to 3/RT. When the capacitor voltage reaches the upper threshold (Ramp Peak), the comparator changes state and the capacitor discharges to the lower threshold (Ramp Valley) through Q1. While the capacitor is discharging, Q2 provides a high pulse. A discharge of the oscillator con be initiated by applying a high level to the Sync pin. A short pulse of a frequency higher than the oscillator's free running frequency can be used to synchronize the ML4811 to an external clock. The pulse can be equal to the desired deadtime (TD) or the deadtime can be determined by IDIS and CT, whichever is greater. The oscillator period can be described by the following relationship: tOSC = tRAMP + tDEADTIME where: tRAMP = and: C (Ramp Valley to Peak) ISET C (Ramp Valley to Peak) IQ1 tDEADTIME = I(1) SYNC 10 ISET 6 3V ISET 5V RT Q2 + V(1) CT 7 IDIS - CLOCK OUT 5 Figure 4. Switching Current and Pin 4 Voltage -- Normal Q1 I(1) CLOCK tD RAMP PEAK V(1) RAMP VALLEY CT Figure 5. Switching Current and Pin 4 Voltage -- Load Fault 100k 100nF 47nF 22nF RT () 0nF 10k 4.7nF 2.2nF 1nF 470pF 1k 100 1k 10k 100k 1M Figure 6. Simplified Oscilator Block Diagram and Timing 160 140 1.0nF TD (ns) 120 100 470pF 80 10k 100k FREQUENCY (Hz) 1M FREQUENCY (Hz) Figure 7. Oscillator Timing Resistance vs Frequency Figure 8. Oscillator Deadtime vs Frequency 6 ML4810, ML4811 ERROR AMPLIFIER The ML4811 error amplifier is a 5.5MHz bandwidth 12V/sec slew rate op-amp with provision for limiting the positive output voltage swing (Output Inhibit line) for ease in implementing the soft start function. OUTPUT DRIVER STAGE The ML4811 Output Driver is a 2A peak output high speed totem pole circuit designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors. 5 4.70 2.20 1.00 0.47 0.22 0.10 0.047 0.47 1 (V) 3 VOUT 2 4 VIN TD (s) 1.0 2.2 4.7 10.0 22 47 100 0 0.2 0.4 0.6 0.8 1.0 CT (nF) TIME (s) Figure 9. Oscillator Deadtime vs CT (3k RT 100k) Figure 10. Unity Gain Slew Rate 100 80 60 AV 40 20 VCC POWER VC 13 AV (dB) Q2 OUT A 11 OUT B 0 0 -20 0 0 -90 -180 100M 14 Q1 POWER GND 100 1k 10k 100k 1M 10M 12 FREQUENCY (Hz) Figure 11. Open Loop Frequency Response Figure 12. Simplified Schematic 7 ML4810, ML4811 3 0.2 IL (A) 0 2 VOUT (V) VSAT (V) SOURCE 15 -0.2 10 1 SINK 5 0 0 0 0.5 IOUT (A) 1.0 1.5 0 40 80 120 160 200 TIME (ns) Figure 13. Saturation Curves Figure 14. Rise/Fall Time (CL = 1000pF) 2 IL (A) 0 ICC -- SUPPLY CURRENT 40 35 30 25 20 15 10 5 VOUT (V) 15 -2 10 5 0 0 100 200 300 400 500 TIME (ns) 0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 15. Rise/Fall Time (CL = 10,000pF) Figure16. Supply Current vs. Temperature 8 ML4810, ML4811 9 ML4810, ML4811 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.02 MIN (0.50 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0 - 15 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 10 ML4810, ML4811 PHYSICAL DIMENSIONS inches (millimeters) (Continued) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.060 MIN (1.52 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0 - 15 0.008 - 0.012 (0.20 - 0.31) Package: S20 20-Pin SOIC 0.498 - 0.512 (12.65 - 13.00) 20 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.007 - 0.015 (0.18 - 0.38) 11 ML4810, ML4811 ORDERING INFORMATION PART NUMBER ML4810CP ML4810CS ML4811CP ML4811CS TEMPERATURE RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C PACKAGE 16-Pin PDIP (P16) (End Of Life) 16-Pin Wide SOIC (S16W) (Obsolete) 20-Pin PDIP (P20) (Obsolete) 20-Pin SOIC (S20)(Obsolete) is a registered trademark of Micro Linear Corporation (c) Micro Linear 1997 Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4810-01 12 |
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